1. Field of the Invention
This invention relates to a field of non-volatile memory devices and, in particular, to apparatus and means for providing a voltage reference that is independent of variations in supply voltage, temperature and process, and, more particularly, to a circuit for minimizing the overshoot problem encountered during memory access and for reducing the access time during the read mode of electrically programmable and electrically erasable read-only memories (EEPROMs) and of electrically programmable read-only memories (EPROMs) having floating gates implemented in metal-oxide-semi conductor (MOS) technology.
2. Art Background
The fabrication of non-volatile memory devices such as EPROMs utilizing MOS technology is well known in the prior art. These EPROMs employ memory cells utilizing floating gates which are generally formed from a polysilicon member completely surrounded by an insulator. Electrical charge is transferred into the floating gate using a variety of techniques such as avalanche injection, channel injection, Fowler-Nordheim tunneling, hot electron injection, etc. A variety of phenomena have been used to remove charge from the floating gates, including exposing the memory to ultraviolet radiation. The floating gate is programmed when the charge is stored in the floating gate. The cell is in unprogrammed, or erase state when the floating gate is discharged.
Because of the complex and time-consuming procedures required to erase EPROMs, these devices have been used primarily in applications requiring read-only memories. Electrically programmable and electrically erasable read-only memories (EEPROMs) were developed to erase and to rewrite the memory devices on a byte-by-byte basis. These EEPROMs have also been referred to as electrically alterable read-only memory. Commercially available EEPROMs have generally used a thin oxide region to transfer the charge into and from a floating gate. In a typical memory, a two-transistor cell is used. For instance, U.S. Pat. No. 4,203,158 discloses the fabrication of such EEPROMs into an array where X and Y select lines provided for the selection, programming, and reading of various EEPROM cells.
As circuitry on a single integrated circuit becomes more complex, establishing bias conditions that are independent of variations in power supply, temperature and process are critical in meeting the performance objective of the circuit. Wide fluctuations in bias current with supply voltages, temperature and process result in an unnecessary power consumption in such circuit. Furthermore, supply independent bias circuitry is required to minimize the injection of spurious high frequency signals from the power lines onto the signal lines. With respect to non-volatile memories, variations in the bias current result in poor frequency response of the sensing circuits and contribute to an undesirable condition called overshoot. Under overshoot, the sensing circuits coupled to the non-volatile memory would read the wrong value, i e., where the sensing circuit is supposed to read a 1 which is an erased EPROM and on account of the slow feedback response, the sensing circuit actually reads 0 before it reads a 1. Thus, variation in the bias current to the non-volatile memory cells results in yield losses, poor access time and at worst, failed devices.
To achieve supply independence, one must refer the bias circuit to some potential other than the supply voltage. In MOS circuits, the choice of biasing circuit includes the use of a threshold voltage V.sub.t, the use of the difference between the threshold voltages of dissimilar devices, .DELTA.V.sub.t, the use of base-emitter voltage V.sub.BE of the parasitic bipolar transistor in CMOS technology, the use of thermo voltage V.sub.T, the use of zener diode, and the use of band-gap voltage V.sub.BG. See, Gray, P. R. and Mayer, R. G., "Analysis and Design of Analog Integrated Circuits", (Wiley: Second Edition, 1984), Chapter 12.3, pages 730-737.